The present invention pertains to semiconductor integrated circuits. In particular, the present invention pertains to an integrated circuit including a nonvolatile memory and a capacitor used as an analog device.
It is often desirable to provide both memory circuitry and analog circuitry on the same integrated circuit. One such desirable integrated circuit may include a nonvolatile memory, such as an EPROM, EEPROM or flash memory, and a so-called low voltage coefficient capacitor. A low voltage coefficient capacitor is a capacitor whose capacitance and/or resistance does not significantly vary with an applied voltage. This is an important characteristic for analog applications and it primarily determines the performance of analog circuits. For example, a parasitic capacitor formed from a depletion region is generally not considered to be a low voltage coefficient capacitor because the capacitance value of such a capacitor is a function of the depletion region, which in turn, is sensitive to the applied voltage. An example of a low voltage coefficient capacitor includes two polycrystalline silicon (poly) capacitor plates separated by a dielectric layer. For both polysilicon electrode plates, the doping level should be very high to avoid the degradation of capacitor voltage coefficient due to the contribution of parasitic depletion capacitance inside the polysilicon films.
FIG. 1 shows a prior art plate capacitor. This capacitor has a top-poly-electrode 15 and a bottom-poly-electrode 13 having an edge 19. As shown, the electrodes 15 and 13 are offset such the edge 19 of bottom-poly-electrode 13 is overlapped by top-poly-electrode 15. Further, this prior art plate capacitor includes substrate 10 (e.g., having an nxe2x88x92 conductivity), a contact diffusion region 11 (e.g., having a p+ conductivity), a field oxide region 12, a dielectric capacitor 14, an interlayer dielectric 18, metal contact regions 16, and a passivation layer 17 (e.g., formed of glass). The configuration of FIG. 1 provides simple connection of metal contacts to each electrode 15 and 13 without risk of short circuit between the electrodes 15 and 13.
For most of the common nonvolatile memory processes, double polysilicon films are utilized for the memory cellsxe2x80x94the first polysilicon for the floating gate and the second polysilicon (normally with metal silicide on top) for the control gate. Unfortunately, the first polysilicon is usually lightly doped to ensure the quality and reliability for the gate oxide beneath the floating gate and for the interpoly dielectric (e.g. ONO layer) between the floating gates and control gates. As a result, with the second polysilicon as the bottom electrode plate and interpoly capacitor, the additional third polysilicon film has to serve as the top electrode plate. In other words, the complicated triple polysilicon process becomes inevitable for the embedded non-volatile memory products in analog applications.
However, formation of such a poly capacitor can be difficult in certain applications. FIGS. 2-6 illustrate a proposed manner of forming such a device. Illustratively, the device formed includes one or more nonvolatile memory cells similar to those designed by Silicon Storage Technologies(trademark). See U.S. Pat. No. 5,242,848. First, a field oxide 12 is formed, e.g., using the well-known LOCOS (local oxidation of silicon) process. According to such a process, a nitride layer such as Si3N4 is deposited on the Si substrate 10, and windows are patterned in the nitride layer in the vicinity at which the field oxide regions are to be formed. The substrate is then heated in the presence of oxygen.
Next, a gate oxide region 14 is deposited or grown on the substrate 10 surface. Then, a first poly layer 16 (poly 1) is deposited on the gate oxide 14. As shown in FIG. 3, the poly layer 16 is patterned to form poly floating gates 18. The poly floating gates 18 typically must be lightly doped. Referring to FIG. 4, poly oxides 20 are grown on the poly floating gates 18 using a second LOCOS step. A thin oxide having dielectric spacers 22 (such as SiO2, Si3N4 or ONO) are also formed on the side surfaces of the poly floating gates 18. Then, a second poly layer 24 (poly2) is deposited on the substrate, i.e., so as to cover the spacers 22, field oxide 12 and poly oxide 20, and gate oxide 14. A metal silicide may also be formed on the poly 2 layer 24 (not shown).
As shown in FIG. 5, the second poly layer is patterned to form control gates 26 on the poly oxides 20 and one of the spacers 22 of each cell. The patterning step also forms a bottom or lower capacitor plate 28 on the field oxide 12. A dielectric layer 30, such as a chemical vapor deposition (CVD) tetraethylorthosilicate (TEOS), CVD-ONO, or other high dielectric materials (e.g., Ta205, etc.) is then deposited on the substrate surface so as to cover the lower capacitor plate 28, field oxides 12 and 20, control gates 26, spacers 22 and gate oxide 14. Then, a third poly layer 32 (poly 3) is formed on the dielectric layer.
As shown in FIG. 6, the poly 3 layer 32 is patterned to form the top or upper capacitor plate 34. Then, the dielectric layer 30 is patterned to form the dielectric region 36 on the capacitor plate 28. Additional steps may be performed for forming the source and drain regions of the memory cells 38, which are not described herein.
The above proposed process for fabricating the combined nonvolatile memory cell and capacitor, however, is difficult to implement for several reasons. First, as shown in FIG. 5, the dielectric layer 30 is applied directly on top of the exposed portions of the gate oxide 15 in peripheral CMOS devices. The dielectric layer 30 is patterned by etching away the unwanted portions of the dielectric layer 30 using a wet etchant. As shown in FIG. 7, this can undercut the oxide 14 in a vicinity of a CMOS gate 40.
More importantly, the overall topographical height by which the memory cell structures protrude from the substrate surface make it very difficult to pattern the poly 3 layer in forming the upper capacitor plate. This is illustrated in FIGS. 8 and 9. FIG. 8 shows an overhead view of a nonvolatile memory cell formed according to the prior art. FIG. 9 shows a cross section through the line Axe2x80x94Axe2x80x2 after the poly 3 layer 32 and dielectric layer 30 have been deposited and prior to patterning the upper capacitor plate and dielectric region. This corresponds to the highest topological height or profile of the substrate prior to the patterning of the poly 3 layer 32. As can be seen, part of the floating gate 18 and poly oxide region 20 overlie a field oxide region 42. In order to describe the topographical issues more clearly, each file thickness is assigned to have a typical value. Here, the average thickness of the poly 3 layer 32 is about a=2700 xc3x85. The average thickness of the dielectric layer 30 (in this example, a CVD-TEOS material) is b=450 xc3x85. The average thickness of the poly 2 control gate 26 is c=3200 xc3x85. The average thickness of the middle of the gate poly oxide region 20 is d=2200 xc3x85. The average thickness of the middle of the floating gate 18 is 500 xc3x85. The height of the field oxide region 42 above the gate oxide layer 14 (which is the lowest point on the substrate surface to which the poly 3 layer 32 and the dielectric layer 30 must be etched) is f=3000 xc3x85.
In patterning the poly 3 layer 32 and the dielectric layer 30, a photoresist material is coated onto the substrate surface. A light beam is then passed through a photolithographic mask which exposes selected portions of the photoresist to the light beam. The non-exposed portions of the photoresist material are then removed. The remaining photoresist portions act as a mask to protect the underlying region from exposure to an etching agent.
In order to properly expose the photoresist material, the light beam must be focused onto a particular area at a certain height or distance normal to the substrate surface. However, due to the high topological variation in the substrate surface height, which variation can be as high as 0.9 xcexcm, it is difficult to focus the light beam at a suitable distance from the substrate surface. This is because some focus distance in the range of the 0.9 xcexcm height variation must be chosen which will be suitable for some portions of the photoresist and unsuitable for others. As such, the photo window becomes very narrow.
Next, consider that the poly 3 layer 32 must be plasma etched. The portion 32xe2x80x2 of the poly 3 layer is much thicker (e.g., a+b+c+d+e+f=1,600 xc3x85) than the portion 32xe2x80x3 of the poly 3 layer (e.g., only a=2700 xc3x85) by a factor of almost 4xc3x97. In order to ensure that no poly stringers remain, the poly 3 layer 32 must be over etched by a factor of as much as 500% or more. This tends to damage the dielectric region of the capacitor and the underlying upper capacitor plate.
It is an object of the present invention to overcome the disadvantages of the prior art.
The invention achieves the above noted object as well as other objects. According to one embodiment, a process is provided for manufacturing a semiconductor device. A lower polycrystalline silicon layer is deposited on a substrate surface and on one or more structures that protrude from the substrate surface. A dielectric layer is formed on the lower polycrystalline silicon layer. An upper polycrystalline silicon layer is deposited on the dielectric layer. The upper polycrystalline silicon layer is patterned to form one or more upper capacitor plates. Next, the exposed portions of the dielectric layer not covered by the one or more upper capacitor plates are removed. After the steps of patterning the upper polycrystalline silicon area and removing the exposed portions of the dielectric layer, the lower polycrystalline silicon layer is patterned to form at least one or more lower capacitor plates. Each lower capacitor plate underlies a corresponding one of the upper capacitor plates and a portion of the dielectric layer covered by the corresponding upper capacitor plate.
Thus, according to the invention, the upper capacitor plate is patterned first, then the exposed portions of the dielectric layer are removed, followed by patterning the lower capacitor plate. Illustratively, such reverse order patterning is possible provided that the upper capacitor plate is made smaller than the lower capacitor plate. By reversing the order in which the plates and dielectric are patterned, the variance in topological height of the to-be-patterned layers during fabrication is reduced. In addition, the lower poly layer from which the lower capacitor plate is formed protects underlying structures and layers, most notably, the thin gate oxide layer of peripheral CMOS device, from etching induced damage that can occur while etching the layer above the lower poly layer, such as the dielectric layer